1) Field of the Invention
The invention is in the field of Integrated Circuits.
2) Description of Related Art
Metal interconnects are utilized in the fabrication of integrated circuits as a means of connecting various electronic and semiconductor devices into a global circuitry. Two key factors considered when fabricating such metal interconnects are the resistance (R) of each metal interconnect and the coupling capacitance (C), i.e. cross-talk, generated between metal interconnects. Both of these factors hamper the efficiency of metal interconnects. Thus, it has been desirable to reduce both the resistance and the capacitance in metal interconnects in order to mitigate the so called “RC-delay.”
For the past decade, the performance of integrated circuits, such as those found on microprocessors, has been greatly enhanced by the incorporation of copper interconnects into the “back-end” of line processing sequence. The presence of such copper interconnects, versus aluminum interconnects, greatly reduces the resistance of such interconnects lending to their improved conduction and efficiency.
Attempts to reduce the coupling capacitance generated between metal interconnects have included the use of low-K (2.5-4) dielectric layers that house the metal interconnects, where K is the dielectric constant of the dielectric layers. However, the incorporation of such films has proven to be challenging. Other attempts to reduce the coupling capacitance between metal interconnects has focused on “air-gap” technologies, where no dielectric layer exists between metal lines. Although this technique has been effective for reducing the coupling capacitance, a result of air having a K-value of only 1, the structural integrity of a plurality of metal interconnects may be compromised in the absence of supporting dielectric layers.
Thus, a method to mitigate the RC-delay in a plurality of metal interconnects is described herein.